Given the consumer electronic product industry's trend toward decreased size, increased portability and convergence of function, electronics manufacturers are confronted with a device integration challenge. Two solutions that have emerged from this issue are system-on-a-chip (SoC) and system-in-a-package (SiP) technologies. The International Technology Roadmap for Semiconductors (ITRS) has identified these approaches as two of the most attractive approaches for 3D packaging. These solutions are being used in a variety of industries, including the computer, consumer, aerospace, military, and medical electronic industries. SoC's and SiP's can be accomplished with a wire bonder or ball bonder.
The first solution, system-on-a-chip (SoC) technology, was designed for applications that require components implemented into a single integrated circuit, such as those applications requiring the lowest power, highest clock rates and lowest unit costs. This single chip can contain a variety of functions including digital, analog, mixed-signal, and RF. The benefits of this technology include a smaller footprint and space requirements, higher performance due to the increased number of circuits on the chip, greater system reliability, lower power requirements, and a potentially lower cost for the end user.
The second solution, system-in-a-package (SiP) technology, was designed for multiple advanced packaging applications that require a fully functional, highly specialized module that can be easily integrated into a system. A SiP includes multiple integrated circuits enclosed in a single package or module. The dies containing the integrated circuits may be stacked vertically on a substrate and connected by wires bonded to the package. Alternative, the dies can be connected through flip chip technology, in which solder or gold ball bumps are used to join stacked chips together. Localizing functionality to a SiP module reduces the complexity and cost of the system board, and removes this design burden from the system designer.
So which technology is better?
The choice between SiP and SoC often creates a debate among RF designers because both approaches provide different advantages for different end-market applications. SiPs allow for relatively easy hetero-integration of analog and RF functionalities with digital CMOS, with possible cost and performance benefits. However, proper system partitioning at the design stage is key to obtaining the maximum value from a SiP. SoCs provide the lowest manufacturing cost, but design costs are often higher and time-to-market is generally slower. Depending on the anticipated unit volumes and target ASPs for the required system, either approach may be desirable.
The objective of RF packaging, where RF (Radio frequency) is the range of electromagnetic frequencies above the audio range and below infrared light (from 10kHz to 300GHz), is to transfer signals while preserving bandwidth (Tummala). This becomes more challenging at higher frequencies because of the wave nature of RF signals. The applications of personal communication, wireless local area networks, satellite communications, and automotive electronics, are providing the driving force for packaging needs at higher frequencies, motivating manufacturers to provide lower cost technology solutions with increasingly higher performance and functionality. In addition, there is a driving force for new products to provide the same functionality at a smaller overall size, lower power and better design, product attributes which are determined through design and manufacture (Zhang, Lec 1).
Why are these attributes important? Take RF power for example, which is the primary measure of a wireless signal. In a receiver, signal strength is a key factor in maintaining reliable communications. In the transmitter, the amount of power transmitted is important for maintaining the range and reliability of the radio link.
It has been our experience, in the Palomar Mircoelectronics lab, that automating the RF Packaging process, even at the ever increasing levels of complexity and minaturization, is possible. Once the process is set up, a single operator can build the needed packages in a cost-effective manner. The operator works with 3 or 4 systems at time: high accuracy wire bonder, a flexible and accurate die bonder and an additional high accuracy die bonder (with an optional configuration for wafer scale packaging). If there is a need for anautomated precision dispenser, that too can be added to the mix. (right: wire bonder performing complex low loops that are often used in RF packaging) Evolution
Wireless technologies have evolved rapidly over the past two decades. Previously large RF/microwave modules have begun to evolve into multi-function systems such as system-on-a-chip (SoC) and sytstem-in-a-package (SiP) methodologies. Many industries are utilizing these technologies. For example, the medical industry is using RF functionalities for pacemakers and other implantable devices. The aerospace and defense industries are creating new communication, surveillance and anti-jamming technologies for the modern battlefield. And industrial RF application developers are improving the real-time monitoring of field and factory operations. (Ebbutt)Trends
There are several trends occurring in RF packaging. The first is variation in levels of integration: an integrated package solution provides a reasonable time to market with good yield, while a fully integrated solution takes a longer time to go to market. Second is to integrate passive components: there has been a decrease in passive components and a move to multilayer devices. Third is to integrate the RF substrate: the RF substrate is moving towards a modular design with integrated components. Finally, there is an increasing trend for RF MEMS as the demand exists for smaller and smaller devices. _______________________________________________________________
Allen, Roger. Shrinking ICs Need High Density In A Package Deal. July 24, 2008. http://electronicdesign.com/Articles/Index.cfm?ArticleID=19340